module pdp8_RAM (
  pdp8_clk,
  pdp8_reset,
  pdp8_addr,
  pdp8_DI,
  pdp8_start_RD,
  pdp8_start_WR,
  pdp8_DO,
  pdp8_RAM_CC
);

input pdp8_clk, pdp8_reset;
input[14:0] pdp8_addr;
input[11:0] pdp8_DI;
input pdp8_start_RD;
input pdp8_start_WR;
output reg[11:0] pdp8_DO;
output wire pdp8_RAM_CC;

reg[11:0] ram [0:32767];
reg busy;
assign pdp8_RAM_CC = ~busy;

always @ (posedge pdp8_clk, pdp8_reset)
begin
  if (pdp8_reset)
    begin
      pdp8_DO <= 0;
      busy <= 0;
    end
  else
    begin
      pdp8_DO <= ram[pdp8_addr];
      if (pdp8_start_RD)
        begin
          busy <= 1'b1;
        end
      else if (pdp8_start_WR)
        begin
          busy <= 1'b1;
          ram[pdp8_addr] <= pdp8_DI;
        end
      else
        busy <= 1'b0;
    end
end

endmodule